This invention relates generally to sigma-delta (SD) modulators and, more specifically, to N-level quantizers used in multi-bit SD modulators.
SD modulators used in analog-to-digital converters (ADCs) and other applications are well known in the art. Reference may be had, by example, to S. R. Norsworthy et al., xe2x80x9cDelta-Sigma Data Convertersxe2x80x9d, IEEE Press, NY, 1997, and to J. G. Proakis et al., xe2x80x9cDigital Signal Processingxe2x80x9d Third Edition, Prentice-Hall, 1996. A typical embodiment of a SD modulator includes a loop filter followed by quantizer, and a digital-to-analog converter (DAC) in the feedback path.
In a SD modulator that outputs multiple bits (multi-bit) the output signal of the loop filter is quantized with a multi-bit quantizer. For example, in a four bit SD modulator the output of the loop filter is quantized into 16 levels. However, quantization into N (e.g.,16) levels requires the presence of Nxe2x88x921 or 15 comparators. As may be appreciated, the use of this many comparators can cause a number of problems. For example, the switching operation of a comparator and/or the operation of a clocked or dynamic output latch can result in the generation of kickback noise, thereby reducing accuracy and also disturbing other circuitry, such as the other comparators and the circuitry that generates the multiple threshold voltages used in the multi-bit quantizer. Also, the input capacitance of the comparators loads the output of the last amplifier in the loop filter, and thus increases its current consumption. Note that relatively large input transistors are typically used in multi-level quantizers to achieve a low offset, as opposed to the relatively simple comparators used in single-bit sigma-delta modulators. Furthermore, the comparators themselves may consume a significant amount of current, as well as integrated circuit area. Note as well that in multi-bit quantizers a continuous time preamplifier is often used to achieve a low offset value, as opposed to a simple, low current drain dynamic latch as is typically found in single-bit quantizers.
A need therefore exists to provide an improved multi-bit sigma-delta modulator, such as a switched capacitor (SC) multi-bit SD modulator, as well as a continuous time multi-bit SD modulator, having an improved quantizer that exhibits a reduced generation of kickback noise, input capacitance and power consumption.
The foregoing and other problems are overcome by methods and apparatus in accordance with embodiments of these teachings.
These teachings provide embodiments of an N-level quantizer for use in an n-order sigma-delta modulator (SDM), wherein the coupling of kickback noise into other circuitry and the input capacitance are both reduced. The reduction in the kickback noise has the beneficial effect of enhancing the dynamic range of the SDM by reducing disturbances and quantization error. The reduced input capacitance of the quantizer reduces power consumption, as the load of the last amplifier of the loop filter is reduced and, thus, the amplifier can be designed to operate with reduced bias currents. A further benefit of these teachings is that the kickback noise is also reduced in the circuitry that generates the required multiple comparator threshold voltages or currents used in the multi-level quantization, thereby enabling simpler and lower power circuits to be employed as compared to conventional approaches, such as switched capacitor circuits used to sample the threshold. In addition, the disclosed circuitry enables a dither signal to be added in a simple manner, thereby reducing the generation of unwanted tones for low input signal levels and improving the dynamic range of the SDM.
An N-level quantizer circuit that is provided in accordance with these teachings has an analog input terminal and Nxe2x88x921 digital output terminals, and includes a sampling circuit coupled to the input terminal for providing a sampled input signal; at least one preamplifier stage for converting the sampled voltage input signal to a current signal and providing an amplified sampled input signal; and Nxe2x88x921 comparator stages each having an input coupled to an output of the common preamplifier stage. Individual ones of the Nxe2x88x921 comparator stages operate to compare the amplified sampled input signal to an associated one of Nxe2x88x921 reference signals. The quantizer further includes Nxe2x88x921 latches, individual ones of which latch an output state of one of the Nxe2x88x921 comparators and have an output coupled to one of the Nxe2x88x921 digital output terminals of the quantizer circuit. Individual ones of the Nxe2x88x921 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise from the Nxe2x88x921 latches to others of the comparators and to the input terminal of the quantizer circuit. The use of the common preamplifier stage also serves to reduce the input capacitance of the quantizer, thereby reducing the capacitive load seen by the output amplifier, which may be an integrator, of the loop filter.
For the purposes of these teachings the output latch may be considered to be an integral part of a comparator, as the latch performs the actual conversion from the analog signal presentation to the digital signal presentation, with the aid of positive feedback. As such, one may consider that a comparator in this context is formed by two common gate current buffers, one for the input signal and the other for the reference signal, and the latch(es) in the output.
The quantizer further includes a dither signal generator having an output coupled to the output of the common preamplifier stage, and a threshold signal generator outputting the Nxe2x88x921 reference signals. The threshold signal generator may be simply constituted using a string of series coupled resistances connected between positive and negative reference voltages.
The disclosed quantizer circuitry may be extended to support a sigma-delta modulator topology with a chain of integrators with weighted forward summation. In this structure the outputs of all of the integrators are first summed in a summer, the output of which is then fed to the quantizer. In the disclosed quantizer structure the summing can be readily implemented in the current mode by providing one linearized preamplifier per integrator, and by wiring the outputs of these preamplifiers together. The current mode dither signal can be connected to this same summing node. The summed current is then fed to the Nxe2x88x921 comparator stages.
The preamplifier stage(s) includes a first differential transistor pair that converts the sampled input voltage signal to a first current signal. Individual ones of the Nxe2x88x921 comparators include an input stage constructed to include first common gate configured transistors that operate to suppress the feedback of noise from the Nxe2x88x921 latches to the input terminal of the quantizer circuit. As all of the common gate transistors may have identical dimensions, and as they all have the same source and gate voltages, the currents through these transistors are equal. Therefore the current is equally divided between the Nxe2x88x921 comparator stages. Individual ones of the comparators also include a threshold input stage constructed using a second differential input transistor pair for converting an associated reference signal voltage to a second current, and to also include second common gate configured transistors operating to suppress the feedback of noise from the Nxe2x88x921 latches to the reference signal generator. The second current is coupled through the second common gate configured transistors and is summed at an output node of the comparator with the first current signal.
The N-level quantizer may form a part of a multi-bit, nth order sigma-delta modulator.
A method in accordance with these teachings for operating an N-level quantizer includes steps of: (a) sampling an input signal to provide a sampled input voltage signal; (b) preamplifying the sampled input voltage signal and outputting a first current signal representing a preamplified sampled input signal; (c) adding a dither current signal to the first current signal to generate a dithered first current signal; (d) coupling the dithered first current signal to an input terminal of individual ones of Nxe2x88x921 comparator stages wherein the current is equally divided between the Nxe2x88x921 comparator stages; (e) operating individual ones of the Nxe2x88x921 comparator stages to compare the dithered first current signal to an associated one of Nxe2x88x921 reference current signals; and (f) latching an output of each of the Nxe2x88x921 comparator stages with a dynamic latch; wherein individual ones of the Nxe2x88x921 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise generated by the step of latching to others of the comparators and to an input terminal of the N-level quantizer.
When these teachings are extended to the case of the sigma-delta modulator topology having a chain of integrators with weighted forward summation, the method operates a combined summer/N-level quantizer by: (a) sampling the plurality of input signals to provide sampled input signals; (b) operating a plurality of preamplifiers for preamplifying the sampled input voltage signals and outputting the first current signals representing preamplified sampled input signals; (c) summing the first current signals by connecting together the outputs of the preamplifiers; (d) adding a dither current signal to the sum of the first current signals to generate a dithered sum of the first current signals; (e) coupling the dithered sum of the first current signals to an input terminals of individual ones of Nxe2x88x921 comparator stages, where the current is equally divided between the Nxe2x88x921 comparator stages; (f) operating individual ones of the Nxe2x88x921 comparator stages to compare the dithered sum of the first current signals to an associated one of Nxe2x88x921 reference current signals; and (g) latching an output of each of the Nxe2x88x921 comparator stages with a dynamic latch. In the preferred embodiment the individual ones of the Nxe2x88x921 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise generated by the step of latching to others of the comparators, as well as to an input terminal of the N-level quantizer.
The step of adding the dither current signal to the first current signal includes a step of generating the dither signal to have pseudorandom fluctuations in amplitude, and a magnitude that varies inversely to the magnitude of the input signal.